ISCAS 2007 will feature the following 9 tutorials. Tutorials will be presented in parallel sessions on Sunday May 27, 2007. All of attendees are strongly encouraged to register in advance for the tutorials. Each person may select one morning tutorial and/or one afternoon tutorial from the following list. No hopping between tutorials is allowed.

To register for a tutorial, please click here.

Morning, Sunday May 27, 9am-12pm

Afternoon, Sunday May 27, 1pm-4pm

Tutorials Details:

Tutorial 1: Integrated Biosensors

Presenter: Dr. Khaled Nabil Salama, Rensselaer Polytechnic Institute, Troy, NY, USA; Arjang Hassibi, University of Texas at Austin, Austin, TX, USA

Location: Norwich Room, Third Floor

Abstract:

We will present the design and implementation of monolithic and hybrid sensors using integrated  circuits, particularly  in CMOS. We will begin by providing the definitions and performance metrics of sensors and a brief overview of various noise processes. Subsequently, we will discuss the advantages and shortcomings of sensors built in silicon-based fabrication processes and examine, in detail, their integrated circuit topologies. Next, we will provide a comprehensive study of the design and analysis of CMOS integrated image sensors, integrated biosensors,  and electronic backbone of MEMS hybrid sensors. Topics include: silicon photodetectors; CCD and CMOS sensor architectures and circuits; Affinity-based detection and biochemical transduction; optical, electrochemical, and mechanical transducer design; integrated microarrays, biochips, and  sensor  SoCs.  We will conclude with a survey of advanced research topics in the area of integrated sensors such as smart sensors, RF-IDs, and nanosensors.

Biography:

Khaled Salama received his BSc degree with honors from the Electronics and Communications Department, Cairo University, Egypt in 1997 and the MSc and PhD degrees from the Electrical Engineering Department, Stanford University, USA in 2000 and 2005 respectively. He was elected to both IEEE Sensors and IEEE BioCircuits technical committees in 2006. He is also the recipient of the 2004 Stanford-Berkeley Innovators Challenge Award in biological sciences. He coauthored 25 papers and 3 pending patents in the areas of high dynamic range CMOS image sensors, 3D image sensors, low-power circuits for intelligent sensors, integrated biosensors, instrumentation and sensor interface architectures and circuits.
 
Arjang Hassibi received the B.S. degree with honors from the University of Tehran, Iran in 1997 and the M.S. and Ph.D. degrees from Stanford University in 2001 and 2005, respectively, all in electrical engineering. From March 2005 to August 2006, he was a Postdoctoral Scholar at the Department of Electrical Engineering at the California Institute of Technology. Since August 2006 he has been with the Department of Electrical and Computer Engineering of the University of Texas at Austin where he is currently an Assistant Professor. He has also held research positions in Barcelona Design, Stanford Genome Technology Center, Panorama Research Institute, and Xagros Genomics which he co-founded in 2001. His main research areas are biosensors and bioelectronics, integrated sensors, DNA and protein integrated microarrays, biomedical VLSI systems, biological assay modeling, noise spectroscopy, and molecular diagnostics.

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Tutorial 2: Satellite Navigation Receiver Design : GPS and Beyond

Presenter: Dr. Andrew Dempster, University of New South Wales

Outline of the Tutorial :

• Introduction to the GPS L1 signal: spectrum, modulation and data. How does CDMA work? What are the strengths and weaknesses of the selected satellite codes?
• How a position can be calculated using GPS. A brief discussion of the least-squares solution.
• Where errors in position come from. What are the six main sources of error and how can they be dealt with?
• How a receiver processes the signal to make measurements. Breaks the receiver into subsystems: antenna, RF front end, digital baseband and processor. What activities happen where?
• New GPS signals: L2C and L5 - how they differ from L1 and what advantages they bring. The new codes and data have been designed to achieve certain advantages over L1 - how good are they?
• New Galileo signals: why are they better? Some elements of the Galileo design are quite radical - what is achieved for instance by the new MBOC modulation?
• Challenges for future satellite navigation receiver design. What can be achieved with the new systems and signals?

Biography:

Andrew Dempster is Director of Research in the School of Surveying and Spatial Information Systems at the University of New South Wales. He has worked in satellite navigation since the late 1980s when he was project manager and system engineer on the development of the first GPS receiver designed and built in Australia. He has given more than 25 courses on GPS and satellite navigation at universities, conferences and company premises. He has several GPS-related patents and his current research interests are satellite navigation system signal processing, reconfigurable receiver design, machine automation, and integration of GPS with new positioning technologies.

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Tutorial 3: Design of Programmable Wireless Networks aka Cognitive Radios

Presenter: Dr. Ramesh Harjani, Dr. Keshab Parhi, Dr. Ahmed Tewfik, Dr. Gerald Sobelman, University of Minnesota, Minneapolis, USA

Location: Ascot Room, Third Floor

Abstract:

The wide proliferation of wireless services and applications with increasing bandwidth needs is rapidly creating a spectrum shortage. However, the problem is caused primarily by inefficient legacy spectrum allocation policies, so that even when some applications suffer from lack of bandwidth, there is idle capacity in other bands. To deal with this challenge, the FCC, ITU and other regulatory organizations have begun to explore an open spectrum policy implemented by programmable wireless networks. Such wireless networks use cognitive, software reconfigurable radios to increase the efficiency of spectrum access. In particular such programmable wireless networks maximize the availability and enhance the quality of service of diverse applications using the most appropriate access network, or an aggregation of such networks, for any given local conditions. A software defined radio (SDR) terminal is essentially a reconfigurable system that can be dynamically programmed in software to reconfigure the characteristics of the hardware through the use of clearly defined APIs residing on top of a flexible hardware layer. The SDRs use different types of hardware to accomplish various communication tasks. In addition to the programmability and flexibility provided by the DSPs and software-driven communication parameters such as modulation, medium access, cryptography, etc, software defined radios also provide field service capability. So, when requirements change, code downloads, upgrades and modifications are relatively easy to execute. Ultimately, the success of the programmable wireless network vision will hinge on its ability to meet the high level needs of users, service providers, network operators and hardware and software developers. Ubiquitous access to applications with proper quality levels, low cost services, user friendliness, fast and open service creation, lifetime and flexibility of equipment, common execution environment, fast product design and manufacturing, to mention a few, translate into well defined technology requirements. In this tutorial we will discuss system, circuit and implementation issues necessary to design a programmable wireless network that meets these requirements.

Biography:

Ramesh Harjani received the Ph.D. degree from Carnegie Mellon University, the M.S. degree from the IIT Delhi and the B.S. degree from the BITS Pilani. He is Professor of Electrical & Computer Engineering the University of Minnesota, a Fellow of the IEEE and was a Distinguished Lecturer of the IEEE CAS Society. He co-founded Bermai, a startup company developing CMOS wireless chips for multimedia applications. He received Best Paper Awards at the 1987 DAC, the 1989 ICCAD and the 1998 GOMAC. He was the winner of the SRC Design Challenge in 2000 and 2003.

Keshab K. Parhi received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He is currently Distinguished McKnight University Professor at the University of Minnesota. Dr. Parhi is the recipient of numerous awards including Fellow of IEEE , F.E. Terman award by the American Society of Engineering Education, IEEE Kiyo Tomiyasu Technical Field Award and IEEE W.R.G. Baker prize award.

Ahmed H. Tewfik received his B.Sc. degree from Cairo University, Cairo Egypt, in 1982 and his M.Sc., E.E. and Sc.D. degrees from the Massachusetts Institute of Technology, Cambridge, MA, in 1984, 1985 and 1987 respectively. He cofounded Cognicity, Inc. He made a number of seminal contributions to statistical signal processing and wireless communications, including the leading proposal to the IEEE 802.15.3a standard. He is the recipient of several awards and honors, including Fellow of the IEEE, IEEE third Millennium award, E. F. Johnson professorship of Electronic Communication and Distinguished Lecturer of the IEEE Signal Processing Society.

Gerald E. Sobelman received a B.S. in physics, from the University of California, LA in 1974. He was awarded M.A. and Ph.D. degrees in physics from Harvard University in 1976 and 1979, respectively. He has held positions at The Rockefeller University, Sperry Corporation and Control Data Corporations. Since 1986, he has been a faculty member at the University of Minnesota. He has published more than 80 research papers, is a co-author of one book and holds 10 U.S. patents. He has has served as an Associate Editor for IEEE Signal Processing Letters.

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Tutorial 4: Circuit Techniques for Operational Amplifier Speed and Accuracy Improvement : Analog Circuit Design with Structural Methodology

Presenter: Dr. Vadim Ivanov, Texas Instruments, Inc., Tucson, AZ, USA; Dr. Igor Filanovski, University of Alberta, Alberta, canada

Location: Rosedown Room, Third Floor

Abstract:

OpAmp is the main analog building block for both the systems on discrete elements and systems on silicon. The parameters of OpAmp often define and limit the overall system performance. CMOS technology provides an opportunity to use more complex structural solutions and circuit techniques to improve OpAmp accuracy, power/speed ratio, to add new functional advantages, like low voltage supply operation capability or rail to rail input without the switching point, everything for negligible additional component cost. The circuit techniques that will be demonstrated during this course were proven in design of leading industrial OpAmps. These techniques are unified by a common structural design approach, based on the following principles:

• system analysis at the high level of abstraction using the graphic tools like signal flow graphs, and generation of the set of equivalent graph modifications,
• equivalent graph transformations to the form when every important parameter in the system or the amplifier is controlled by a dedicated feedback loop;
• stability of these loops is achieved without compensation capacitors, by using one-stage (preferably current) amplifiers,
• system synthesis consists of implementation of the set of the gain structure modifications followed by simulations based on available library of cells, and final selection of the best circuit solutions.

The particular topics covered in this tutorial include: 

• amplifier gain structure for high speed and gain;
• gain boosting in single and two-stage OpAmp structures and elimination of gain erosion due to the drain-body leakage in single-well process;
• design of the rail-to-rail input stages:
  • NMOS/PMOS stages with stabilized transconductance,
  • PMOS stage with low-noise charge pump for the tail current source,
  • Using the low-Vt transistors to eliminate the switching point;
• CMRR and PSRR improvement:
  • design of high quality tail current source,
  • cascoding of the input pair,
  • class AB output stage design;
• slew rate boost techniques;
• overload recovery time improvement;
• design techniques for 0.9 V power supply;
• using advantages of modern processes implementing different types of transistors.

Biography:

Vadim Ivanov: MSEE 1980, Ph.D. 1987, both from the Institute of Electrical Engineering, St. Petersburg, Russia. Dr. Ivanov worked in Leningrad, and investigated, designed and developed electronic systems and ASICs for naval navigation equipment from 1980 to 1991, and mixed signal ASICs for sensors, GPS/GLONASS receivers and motor control from 1991 to 1995.Dr. Ivanov joined Burr Brown Corp. (presently Texas Instruments Inc., Tucson) in 1996 as a senior member of technical staff, where he is involved in design of the operational, instrumentation, and power amplifiers, voltage references and switching and linear voltage regulators. Dr. Ivanov has 33 US patents, with more pending, on analog circuit techniques. He is the author and coauthor of more than 30 technical papers and three books: Integrated Power Amplifiers (Leningrad, Rumb, 1987), Analog system design with ASICs (Leningrad, Rumb, 1988), both in Russian, and Operational Amplifier Speed and Accuracy Improvement, Kluwer, 2004.

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Tutorial 6: Design Challenges and Solutions for Nanoscale Memories

Presenter: Dr. Ramalingam Sridhar, University at Buffalo, (SUNY), Buffalo, NY; Dr. Praveen Elakkumanan, IBM Semiconductor R & D Center (SRDC); Dr. Sreedhar Natarajan, Emerging Memory Technologies Inc

Location: Durham Room, Third Floor

Abstract:

Static Random-Access Memory (SRAM) is a dominant memory technology for embedded CMOS-memory applications. As device channel lengths shrink down to tens of nanometers, SRAM designs meet new issues and challenges that require changes in the way designs are done. The goal of the tutorial is threefold:

1. Present the design challenges and summarize various circuit-design techniques for  low leakage and high performance memory design;
2. A detailed discussion on SRAM failure mechanisms to understand the impact of process variations, soft errors, leakage and noise on different memory operations; the speakers will reexamine these scaling issues, their impact on cell operation and stability, and design for manufacturability within these constraints; and
3. Discuss future and emerging memory technology trends and what they may mean for low power and robustness concerns — with an emphasis on those aspects that are relevant to SRAM designers.

Biography:

Ramalingam Sridhar received a B.E. (Honors) degree in Electrical and Electronics Engineering from Guindy Engineering College, University of Madras in 1980, MS and PhD in Electrical and Computer Engineering from Washington State University in 1983 and 1987 respectively. Since 1987 he has been with the University at Buffalo, The State University of New York, where he is currently a faculty member in the Department of Computer Science and Engineering. His research interests are in deep submicron VLSI design, low leakage, low noise Circuits, Clocking and Synchronization, interconnects, memory circuits and architecture, and wireless networks security. He has eleven patents and over ninety publications in these areas. He is a senior member of the IEEE and a member of Association of Computing Machinery. He has served as the Program Chair and as the General Chair of ASIC/SoC Conferences.

Praveen Elakkumanan received his B.E (Honors) degree in Electrical and Electronics Engineering from Birla Institue of Technology & Science (BITS), Pilani, India. He received his M.S and Ph.D degrees in Computer Science and Engineering from University at Buffalo (SUNY). His research interests are on leakage analysis, leakage reduction, process variability, and soft errors in high performance and low power SRAM designs. He received the best poster award at the IBM Austin Conference on Energy Efficient Design (ACEED), 2005 for the paper titled “SRAM Designs to Reduce Gate and Subthreshold Leakage Power in the Nanometer Domain”. He has also worked as a software engineer for 2 years and as a supplemental employee at IBM Austin Research Lab. He is currently with IBM Semiconductor R & D Center working on advanced DFM & physical design methodologies for future technologies.

Mr. Sreedhar Natarajan is currently the President and CEO of Emerging Memory
Technologies Inc.  Mr. Natarajan has a combined experience of 15 years in semiconductor memory design and his experience includes working for Paradigm Technology, Texas Instruments, MoSys previously in the areas of SRAM, DRAM, FRAM and Memory Compilers.  Mr. Natarajan serves on various international conference committees like ISSCC, CICC, ESSCIRC, ISLPED, SOC, VLSI Symposium and also currently serves on the IEEE Standards board (NesCOM). He has been an invited speaker at various IEEE international conferences and academic institutions and is hosted many panel discussions and tutorials at major international conferences like ISSCC, CICC and VLSI Symposium. Mr. Natarajan is also the Guest Editor for IEEE Journal of Solid State Circuits for CICC 2003/2004 and ISSCC2004. Mr. Natarajan is the recipient of the IEEE Circuits and Systems Outstanding Service Award'01 and the past chairman for the Dallas Chapter of the IEEE-Solid State Circuits. Mr. Natarajan has co-authored the book "SOI Design: Analog, Memory and Digital Design" and has over 25 patents to his credit. He is a very strong advocate on new and emerging Memory Technologies to the semiconductor memory industry. Mr. Natarajan obtained his Master's degree in computer engineering from University of Southwestern, Lafayette, LA and is a senior member for the Institute of Electrical and Electrical Engineers.

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Tutorial 8: Wireless Sensor Networks: From Theory to Practice

Presenter: Dr. Martin Haenggi, University of Notre Dame, Indiana, USA

Location: Ascot Room, Third Floor

Abstract:

Wireless sensor networks combine distributed sensing, computing, and wireless communications into a powerful technology that offers unprecedented resolution, unobtrusiveness, and autonomous operation for countless applications. At the same time, they offer numerous challenges, in particular the strict energy constraints, the distributed operation, and the scalability. This tutorial provides a comprehensive and self-contained introduction to wireless sensor networks, covering all the relevant aspects from the basic theory to real-world applications. It consists of four parts:

1. Introduction: Motivation, relevance, and important applications
2. Challenges and solutions: Difference to other wireless networks; modelling issues; energy-efficient network protocols; performance limits and quality-of-service issues
3. Practical aspects: Hardware overview; experimental results and measurements.
4. Conclusions and outlook.

Biography:

Martin Haenggi is an Associate Professor of Electrical Engineering at the University of Notre Dame. He completed his doctoral work at the Signal and Information Processing Laboratory of ETH Zürich, Switzerland, in 1999. Before joining Notre Dame in 2000, he spent a postdoctoral year at the University of California at Berkeley. His main research interests are wireless ad hoc and sensor networks. He has published more than 50 articles on ad hoc and sensor networks, covering a broad range of topics from the mathematical theory to experimental work and applications. He currently serves on the Editorial Board of the Elsevier Journal on Ad Hoc Networks, and from 2005-06, he was as a Distinguished Lecturer on sensor networks for the CAS society. In 2005, he received an NSF CAREER award, and he is the principal investigator on several other awards from NSF and DARPA on sensor network-related projects.
Homepage: http://www.nd.edu/~mhaenggi

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Tutorial 12: Challenges and Opportunities of Digital Design in Nanoscale CMOS

Presenter: Dr. Ching-Te Kent Chuang, IBM, New York, USA

Location: Norwich Room, Third Floor

Abstract:

This tutorial reviews the challenges and opportunities of high-performance digital design in nanoscale CMOS technologies. The device structure evolution, material enhancement, and major design challenges are discussed. Examples of logic circuit and SRAM design techniques to overcome the challenges and to mitigate various performance/reliability constraints in conventional planar CMOS technology are given.  Scaled/emerging technologies such as scaled PD/SOI, UT/SOI, strained-Si channel device, hybrid orientation technology, and multi-gate FinFET are addressed with particular emphases on the implications and impacts on circuit design. Finally, novel logic circuit, SRAM, and power-gating schemes exploiting unique structures and properties of emerging devices are discussed.

Biography:

Ching-Te Chuang received the B.S.E.E. from National Taiwan University, Taipei, Taiwan in 1975 and Ph.D. degree in Electrical Engineering from University of California, Berkeley, CA in 1982.

From 1977 to 1982 he was a research assistant in the Electronics Research Laboratory, University of California, Berkeley, working on bulk and surface acoustic wave devices.  He joined the IBM T. J. Watson Research Center, Yorktown Heights, NY in 1982, working on scaled bipolar devices, technology, and circuits. From 1986 to 1988, he was Manager of the Bipolar VLSI Design Group, working on low-power bipolar circuits, high-speed high-density bipolar SRAMs, multi-Gb/s fiber-optic data-link circuits, and scaling issues for bipolar/BiCMOS devices and circuits. Since 1988, he has managed the High Performance Circuit Group, investigating high-performance logic and memory circuits.  Since 1993, his group has been primarily responsible for the circuit design of IBM’s high-performance CMOS microprocessors for enterprise servers, PowerPC workstations, and game/media processors. Since 1996, he has been leading the efforts in evaluating and exploring scaled/emerging technologies, such as PD/SOI, UT/SOI, strained-Si devices, hybrid orientation technology, and multi-gate/FinFET devices, for high-performance logic and SRAM applications.

Dr. Chuang served on the Device Technology Program Committee for IEDM in 1986 and 1987, and the Program Committee for Symposium on VLSI Circuits from 1992 to 2006. He was the Publication/Publicity Chairman for Symposium on VLSI Technology and Symposium on VLSI Circuits in 1993 and 1994, and the Best Student Paper Award Sub-Committee Chairman for Symposium on VLSI Circuits from 2004 to 2006. He was elected an IEEE Fellow in 1994 “For contributions to high-performance bipolar devices, circuits, and technology". He has authored many invited papers in international journals such as International J. of High Speed Electronics, Proceedings of IEEE, and IEEE Circuits and Devices Magazine.  He has presented numerous plenary, invited or tutorial papers/talks at international conferences such as International SOI Conf., DAC, VLSI-TSA, ISSCC Microprocessor Design Workshop, VLSI Circuit Symposium Short Course, ISQED, ICCAD, APMC, and VLSI-DAT, etc.  He was the co-recipient of the Best Paper Award at the 2000 IEEE International SOI Conference.  He holds 18 U.S. patents with another 18 pending.  He has authored or coauthored over 235 papers.

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Tutorial 13: Analog Circuit Design on Digital CMOS : Why it is difficult, and which ideas help?

Presenter: Dr. Hanspeter Schmid, University of Applied Sciences, NW, Switzerland

Location: Rosedown Room, Third Floor

Abstract:

This tutorial covers a wide range of small things an analog-IC designer should know to find a path through all the challenges of designing analog circuits on standard digital CMOS processes. The three main topics are: signal integrity (handling noise, treating signal ground, dealing with parasitic modulated feedback in switched circuits) unconventional use of standard parts (exploiting weak inversion, exploiting small dimension effects, unconventional uses of switched-capacitor techniques), and the question whether to feed back or not to feed back (self-biased and regulated current mirrors for gain enhancement, reduction of power consumption with low-feedback circuits.)  Most examples come from low-voltage and low-noise broad-band applications, but RF is not covered.  Many of the tricks were proven in industrial chips by the author or by people he knows, and will therefore need to be presented without explicit references.

Biography:

Hanspeter Schmid did his doctoral work at the Signal and Information Processing Laboratory of ETH Zürich, doing research on video-frequency amplifiers and filters.  In 2000 he joined Bernafon AG, Bern, where he worked in an international development team doing hearing-aid platforms. Since it was a relatively small team, he designed and improved a very wide range of different circuits, and was responsible for full-system stability and signal integrity on chip set and PCB. Since 2005, he is a research fellow and industry consultant at the Institute of Microelectronics of the University of Applied Sciences North-Western Switzerland.  His main research interests are low-power high-speed circuits and systems.

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Tutorial 14: Design of Digital Filters Satisfying Prescribed Specifications

Presenter: Dr. A. Antoniou, Professor Emeritus

Location: Warwick Room, Third Floor

Abstract:

In a typical digital filter or digital signal processing class, students are asked to design a digital filter of a specified type and fixed order. The design may or may not be satisfactory for any application but almost always in industry, the best design is required that would satisfy certain desired specifications which are usually predefined on the basis of system considerations. Unfortunately, more often than not the topic of designing the best filter for the application is not treated in the classroom. In this tutorial, design methodologies will be described that would yield FIR as well as IIR filters that would satisfy prescribed specifications. Two types of designs will be explored. Closed-form methods based on some classical techniques and iterative methods based on optimization. The tutorial will draw heavily from the proposer's past teaching experience and research results such as the design of elliptic IIR digital filters, optimization-based techniques such as the design of equalized IIR filters using quasi-Newton methods, and the use of enhanced Remez methods for the design of FIR filters that would satisfy precise predefined specifications.

Participants will receive a free license of Dr. Antoniou’s DSP software D-Filter (see http://www.d-filter.ece.uvic.ca for details.)

Biography:

Andreas Antoniou is a Fellow of the IET (previously known as IEE) and the IEEE. He taught at Concordia University from 1970 to 1983, was the founding Chair of the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada, from 1983 to 1990, and is now Professor Emeritus. He is the author of Digital Signal Processing: Signals, Systems, and Filters published by McGraw-Hill in 2005 and the co-author with Wu-Sheng Lu of Optimization: Algorithms and Applications to be published by Springer in the near future. Dr. Antoniou served as Associate/Chief Editor for IEEE Transactions on CAS from 1983 to 1987, as Distinguished Lecturer of the IEEE SP Society in 2003, as General Chair of the 2004 ISCAS, and is now serving as Distinguished Lecturer of the CAS Society. He received the Ambrose Fleming Premium for 1964 from the IEE (best paper award), a CAS Golden Jubilee Medal, and the IEEE CAS Technical Achievement Award for 2005.

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